IBIS Macromodel Task Group

Meeting date: 23 Jan 2007

Members (asterisk for those attending):
* Arpad Muranyi, Intel Corp.
* Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
* Doug White, Cisco Systems
  Hemant Shah, Cadence Design Systems
* Ian Dodd, Mentor Graphics
  Joe Abler, IBM
* John Angulo
  John Shields, Mentor Graphics
  Ken Willis, Cadence Design Systems
  Kumar, Cadence Design Systems
* Lance Wang, Cadence Design Systems
  Luis Boluna, Cisco
* Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
  Patrick O'Halloran, Tiburon Design Automation
  Paul Fernando, NCSU
* Randy Wolff, Micron Technology
* Richard Ward, Texas Instruments
  Sanjeev Gupta, Agilent
  Shangli Wu, Cadence
* Stephen Scearce, Cisco Systems
  Syed Huq, Cisco Systems
* Todd Westerhoff, SiSoft
* Walter Katz, SiSoft
  Vuk Borich, Agilent
  Vikas Gupta, Xilinx

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Opens:

Mirmak: EETimes: Kicking up EDA
- Broadcom official, Humin Moshar
- Work with Mentor on high end C++
- Doing analog in Matlab

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Review of ARs:

- Michael Mirmak try to reserve room until 7:00 PM
  Done
  Ian will handle food arrangements.

- Todd have presentation for review by next meeting
  Done

- Todd update DesignCon IBIS Summit Presentation, add HSpice resolution to it
  Done

- Arpad: Check into what is in the Mentor SystemVision SPICE2VHDL-AMS library
  Done

- Mike: update macro library documentation
  A rewrite was lost. Started over again.

- Arpad: Write parameter passing syntax proposal for a possible BIRD
  TBD

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New Discussion:

Mentor SPICE2VHDL-AMS library
- Provides VHDL-AMS code for most SPICE elements
- Has elements that our macro library does not

Review of Todd's IBIS-AMS presentation for IBIS summit
- Page 6:
  - "Cadence invited to propose" changed to "Open invitation"
- Page 7:
  - Diagrams TBD
  - Title cange to "Circuit Simulation vs. Signal Processing"
  - Add "Pulse Response" bullet
- Page 8:
  - Change to "Secondary / deployment issue"
- Page 9:
  - Discussion on long URLS; decided to leave it.
- Page 10:
  - Add target audience "Silicon/circuit designers"
  - Arpad: Does Cadence really have the only proposal? How about VHDL?

AR: Todd finish presentation and send to Bob by tomorrow

We decided to skip the API discussion.

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Next meeting: IBIS summit, Thursday 01 Feb 2006 05:00pm PT